1. Technical Field
The present inventions relate to systems with variable link widths.
2. Background Art
Various arrangements for memory chips in a memory system have been proposed. For example, in a traditional synchronous dynamic random access memory (DRAM) system, a memory controller and memory chips communicate data through bidirectional data buses and receive commands and addresses through command and addresses buses. The memory chips have stubs that connect to the buses. In some memory systems, the undirectional or bidirectional are point to point interconnects.
In some memory systems, a memory chip receives signals and repeats them to a next memory chip in a series of two or more memory chips. In some of these systems, the last memory chip in the series can send a signal directly back to a memory controller or other originating chip. This is referred to as a ring.
Links between a memory controller and memory chips may be single ended (one conductor) or differential (two conductors carrying complementary signals).
There are various types of transmitters and receivers. Some include delay locked loops to provide clock or strobe signals. Some involve phase interpolators.
Various low power states have been used to reduce power consumption of circuits. These involve reducing voltages or frequency to some or all circuits in a chip or completely shutting off power to portions or all of a chip.
Memory modules include a substrate on which a number of memory chips are placed. The memory chips may be placed on only one side of the substrate or on both sides of the substrate. In some systems, a buffer is also placed on the substrate. For at least some signals, the buffer interfaces between the memory controller and the memory chips on the module. In such a buffered system, there is different signaling (for example, frequency and voltage values, and point-to-point versus a multi-drop arrangement) between the memory controller and the buffer than between the buffer and the memory chips.